1. Field of the invention
The present invention relates to a method for manufacturing a semiconductor device and more particularly to a method for manufacturing a through hole electrically connecting two interconnecting layers together.
2. Description of the prior art
As semiconductor devices have been largely integrated, the width and the spacing of an interconnecting layer electrically connecting elements together have been reduced. In particular, a gate array or the like has a standardized interconnecting layer channel and thus needs to reduce this interconnecting layer pitch for improving the degree of integration. In general, the interconnecting layer pitch is decided by the size and the alignment accuracy of the through hole connecting two different interconnecting layers.
FIG. 1 and FIG. 2 show the first conventional semiconductor device. An underlying interconnecting layer 102 is formed on a semiconductor substrate 101 forming an element, not shown. In this case, the underlying interconnecting layer 102 has a wide pad 102a at the place where a through hole is to be formed. And formed on the underlying interconnecting layer 102 is an inter-layer insulating layer 103 in which a through hole TH is formed. And then formed in the through hole TH is a conductive layer 104 on which an overlying layer 105 is formed. But a margin M between the interconnecting layer and the through hole TH is provided so that the through hole TH may not be bigger than the pad 102a of the underlying interconnecting layer 102, thereby improving a yield. As a result, the interconnecting pitch P of the underlying interconnecting layer 102; EQU P=2 M+H+D
where H is the size of the through hole TH which is decided by taking into account an electromigration-resistant parasitic resistance and D is the minimum interconnecting spacing which is decided by taking into account the limit of manufacturing accuracy and the parasitic capacity to the adjacent underlying interconnecting layer.
The reason why the conventional semiconductor device needs the margin M between the interconnecting layer and the through hole is hereinafter described. As shown in FIG. 1, the pad 102a having the margin M is formed on the underlying layer 102 at the position where the through hole is formed. If the pad 102a does not have the margin M, the width of the underlying interconnecting layer 102 is the same as the width of the through hole TH. In this case, if a mask patterning for forming the through hole is not correctly made in position, the through hole is also formed on the other part of the underlying interconnecting layer 102; in other words, since the through hole is formed with the underlying layer as an etching stopper, if the mask patterning is not correctly made in position, there happens a portion where the etching stopper does not exist, which consequently forms a deeper through hole. To be more specific, a groove deeper than a usual through hole is formed along the side of the underlying interconnecting layer. This groove has narrow spacing and deep shape. When conductive material is implanted in the through hole with this groove formed, the conductive material cannot be implanted in the groove but the gas is hermetically packed in the groove. If there is the space where the gas is packed, breakage or the like will occur in the following manufacturing process and be a cause of a low yield. Therefore, the conventional semiconductor device has a margin between the interconnecting layer and the through hole such that the groove may not be made on the side of the interconnecting layer even if the mask patterning is not correctly made in position.
As such, the first conventional semiconductor device has a problem that the existence of the margin M between the interconnecting layer and the through hole makes the underlying interconnecting layer pitch larger and thus results in lowering a degree of integration.
The second conventional semiconductor device shown in FIG. 3(a)-FIG. 3(e) has been known as a semiconductor device which reduces the interconnecting pitch by removing above-described margin M between the interconnecting layer and the through hole (Japanese Published Unexamined Patent Application No. 64-35937). Firstly, referring to FIG. 3(a), an underlying interconnecting layer 202 is formed on a semiconductor substrate 201 forming an element, not shown, and moreover an inter-layer insulating layer 203 is formed on the whole of them. Further, the thickness of the inter-layer insulating layer 203 is smaller than that of the underlying interconnecting layer 202.
Next, referring to FIG. 3(b), the inter-layer insulating layer 203 is selectively removed from the underlying interconnecting layer 202a and the vicinity of it.
Next, referring to FIG. 3(c), the inter-layer insulating layer 204 is additionally formed on the whole of them.
Next, referring to FIG. 3(d), the inter-layer insulating layer 204 is etched back to expose the underlying interconnecting layer 202a. The condition of this etching-back is a condition in which the selection ratio of the inter-layer insulating layer 204 is larger than that of the inter-layer insulating layer 203; consequently, the inter-layer insulating layer 203 remains. Lastly, referring to FIG. 3(e), an overlying interconnecting layer 205 is formed and connected to the underlying interconnecting layer 202a.
As such, the second conventional semiconductor device does not have the margin between the interconnecting layer and the through hole.
However, in above-described second conventional semiconductor device the thickness of the inter-layer insulating layer 204 cannot be made larger than those of the underlying interconnecting layers 202a, 202b, and consequently, the parasitic capacity between the overlying interconnecting layer 205 and the underlying interconnecting layer 202b is made larger; this therefore produces a problem that the operating speed of the circuit is made lower and also produces a problem that since the overlying interconnecting layer 205 has an uneven surface, it is difficult to make a fine interconnecting and multi-layers of the interconnecting.